With the demand of the liquid crystal panel, high aperture ratio and high resolution (Pixel Per Inch, PPI) became the important goals of the panel design. With the higher PPI, the pixel size is smaller. Due to the height of the post spacer (PS), whether it is photo alignment or rubbing alignment, the height makes the alignment with some blind area, therefore the bottom of the PS needs to use the black matrix (BM) to block the dark line caused the liquid crystal disorder by the poor alignment. Thus, as should not affect the aperture ratio, the position of the PS in the Pixel is very critical. Generally, we choose the PS standing in the middle of two thin film transistors (TFT), refer to FIG. 1, the PS 11 is arranged between the two holes of the organic transparent insulating layer (PLN) 12. The bottom of PS 11 is blocked by the BM 13, the bottom of the data line 14 is also blocked by the BM 13. In the generally design, after group the TFT and the CF, since the pixel size is small to allow narrowing the range of the precision to the group, the PS is easily to slide in the left and right sides of the PLN hole, resulting in PS ratio too small, insufficient support and related adverse. In FIG. 2, although move up the PS 11 may avoid the hole of the PLN 12, the bottom of the PS 11 in the dashed box 15 is also blocked by the BM 13, losing the aperture ratio.